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Semiconductor System-Level Test: 4 Simple Steps to Deployment

As we've already seen, system-level testing (SLT) is a vital semiconductor testing methodology that's also been recognized by leading chipmakers to be both affordable and easily adoptable in high-volume-manufacturing (HVM) scenarios.

But what does a typical SLT deployment look like in an industry where generic, off-the-shelf solutions simply won't suffice and reduced cost of test (CoT) is a top priority?

Let's take a look at a "typical" SLT deployment as exemplified by the fourth-generation ATS 5034 SLT Platform. We'll also briefly examine how Astronics Test Systems' tight collaborative approach to the SLT deployment process contributes to optimal CoT in the near- and long-term.

The Journey Begins

SLT itself may be a highly advanced, next-generation testing methodology, but a typical SLT deployment evolves out of clear and logical "building blocks," with the results of each stage informing and optimizing the next.

With Astronics, an SLT deployment starts with the single-site device development board (DDB) kit. This consists of two components: a supervisory PC and a socket interface board (SIB). The supervisory PC establishes communication between the device under test (DUT) and the tester platform; the SIB incorporates a manufacturer's reference design and test socket. This initial stage also introduces ActivATE™, a robust test development and sequencing software framework designed by engineers for engineers.

Next Steps

Once the DDB kit has been tailored to meet the requirements of the DUT, there's an incremental leap to Astronics' single-slot tester (SST). This single slot accommodates a test interface board (TIB) that itself holds multiple DUTs via a test socket. Optional independent thermal control (i.e., cold, hot, room temperature) on a site-by-site basis is also possible in the SST.

It’s often at this stage that manufacturers can better visualize how the SLT insertion will complement—or even replace—traditional automated testing equipment (ATE) and conventional structural test (ST) and functional test (FT) methodologies in the final testing workflow.

Multiple Slots, Massive Parallelism

The SSTs are then scaled upward to meet demanding HVM applications and deliver SLT's unique synthesis of mission test coverage with output as high as 5,000 units per hour (UPH) per tester. The Astronics hardware that enables massive parallelism is the MSC, or multi-slot chamber, which can be designed to suit manual, semi-automatic, or fully automatic configurations.

For many of Astronics' HVM partners, the SLT deployment culminates in the ATS 5034, a turnkey solution that couples the MSC with an integrated, high-speed handler to fully automate every step of the SLT workflow, including DUT (un)loading and TIB (de)population. This helps to create an SLT platform with the lowest CoT.
Workflow-Diagram FINAL

A Collaborative Approach

Regardless of configuration, the SLT platform relies on customer-furnished equipment (CFE) in the form of the test socket, reference design, and test plan. Different SLT solution providers take different approaches to CFE and third-party integration depending on their expertise and in-house resources.

For its part, Astronics takes a collaborative, mutually transparent approach to the entire SLT deployment process. Before the first DDB kit is even delivered, engineers from both sides meet to discuss important manufacturing goals such as product ramp (volume) and the time-to-volume (TTV) intercept point.

This ongoing and open, albeit confidential, dialogue continues with regular meetings between project managers, system engineers, and test architects. What the companies learn is then applied to the next stage in an iterative fashion. Astronics therefore not only shares but internalizes the manufacturer's goals in order to become a trusted partner in the supply chain for the initial DUT.

SLT in Six Months

Despite its intricacy, the path to massively parallel SLT can usually accommodate a typical ramp target of just six months.

This puts manufacturers in the enviable position of achieving the lowest CoT in the shortest amount of time while also benefitting from a customized, 100% massively parallel SLT solution. Their tester configurations can also be adapted to new test times and product mixes, thereby increasing their lifespan and the solution's overall ROI.

Our C-Brief #3 on this topic lays out the typical SLT deployment process in more detail and explains the optimizations and advantages that are involved in each stage. If you have questions about SLT deployments or SLT in general, please get in touch with us.