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Test & Simulation Feature Stories

Semiconductor System-Level Test: How it Fits into Your Test Workflow

In high-tech, high-volume manufacturing (HVM), device-makers have long implemented a fairly standardized semiconductor testing process: wafer sort (WS), then burn-in after packaging (BI), followed by a combination of structural testing (ST) and functional testing (FT) through the use of automated testing equipment (ATE).

More and more leading device-makers are improving upon this traditional semiconductor testing workflow by adopting system-level testing, or SLT. Whereas some of their approach is driven by industry-specific trends like FinFET migration or heterogeneous packaging, the attractiveness of SLT is apparent to any company manufacturing devices with integrated circuits (ICs) that are influenced by Moore's Law.

This raises an obvious question: if the testing process is already well established, how can a next-generation testing methodology like SLT be integrated smoothly and seamlessly?

Preparing today's workflow for tomorrow's devices

In general, the testing workflow after wafer fabrication begins with WS, the wafer-level test process that separates good from bad die before the dicing operation. After packaging, the chip undergoes BI to screen for infant mortalities in line with previously generated reliability bathtub curves. The final step involves ATE running ST and FT to remove any further process and product defects before shipment.

Early adopters have typically placed SLT in the workflow's final stage, where it can plug any holes left by ATE. Understandably, though, there is considerable pressure to maintain or further reduce cost of test (CoT) by streamlining the testing workflow instead of simply adding another insertion. This streamlining can be achieved by using SLT's unique strengths to consolidate or even replace certain stages of the workflow, thus renormalizing the overall cost distribution.
Future Workflow diagram

More test coverage, more efficiency

The ability of SLT to test complex devices in mission mode at high speed results in expanded test coverage and strategic fault-finding that's much better suited to handle the next wave of system-on-a-chip (SoC) and system-in-package (SiP) devices. This makes it more efficient to transfer testing time to SLT that's typically been allotted to ATE instead.

Likewise, SLT at hot can substitute for BI and even accelerate infant mortalities with hot at-speed testing. Advanced SLT solutions like the ATS 5034 SLT Platform also have an optional tri-temperature thermal feature that allows low-, room-, and high-temperature testing stations to be combined into a single insertion.

The possibilities for workflow optimization through SLT are endless, as are the ways in which costs can be redistributed across the discrete stages to achieve greater test coverage at similar or even lower CoT.

Toward 100% SLT optimized implementation

There's little doubt that the semiconductor ecosystem will continue to evolve as transistor counts and complexity grow while geometries shrink — and as market pressures impel HVM manufacturers to find further efficiencies and ROI around every corner. SLT is well positioned to play a more pivotal role in those testing and optimization processes.

What makes SLT not only attractive but utterly essential in future HVM implementations is massive parallelism, or testing hundreds of devices at the same time on a single machine. The ATS 5034 SLT Platform, for example, is capable of triple-digit massive parallelism, achieving unit per hour (UPH) rates of 5,000 per machine.

This unprecedented fusion of massive parallelism, testing workflow consolidation, and combined defect capture/overkill recovery through 100% optimized SLT means that device manufacturers can maximize their test coverage and improve yields without sacrificing ROI, speed, or volume.

If you'd like to get a better idea of where SLT belongs in your optimized testing workflow, contact Astronics Test Systems today for a free confidential consultation.

We also recommend taking a look at our growing library of C-Briefs, which are short, four-page articles that examine various aspects of SLT — everything from economics to engineering. C-Brief #2 explains the topic covered in this blog post in more detail through additional workflow and consolidation examples.